1. Field of the Invention
The present invention relates to a variable gain amplifier and a differential amplifier. Particularly, the present invention relates to a variable gain amplifier and a differential amplifier, which comprise a signal amplifying transistor and gain control transistors at an output side and a non-output side, whose emitters are both connected to the collector of the signal amplifying transistor.
2. Description of the Related Art
FIG. 6 shows, as conventional art 1, a simulation circuit diagram of a differential amplifier, which comprises two variable gain amplifying circuits of a conventional type. The differential amplifier having this circuit has the amount of negative feedback to signal amplifying transistors 3a and 3b changed according to the amount of currents in output transistors 4a and 4b. Particularly, this differential amplifier has a problem that almost no negative feedback functions when the gain is attenuated to the lowest level possible.
The results of operation simulations on the variable gain differential amplifier of FIG. 6 conducted by changing a gain control voltage (Vagc) of the amplifier will now be explained. FIGS. 7A to 7D are graphs respectively plotting the input transmission characteristic (hereinafter referred to as S21) of the S parameter, noise figure (hereinafter referred to as NF), the input reflection characteristic (hereinafter referred to as S11) of the S parameter, and third order input intercept point (hereinafter referred to as IIP3) indicating intermodulation distortion characteristic, which were observed at 50 MHz, 300 MHz, and 550 MHz. In the simulation of the circuit of FIG. 6, a DC voltage Vbias+Vagc was applied at the node 9, while a DC voltage Vbias−Vagc was applied at the node 10, giving a DC voltage difference across the nodes 9 and 10 by 2Vagc. Simulation results in FIGS. 7A to 7D were plotted against Vagc by the unit of volt (V). The half of the sum of the DC voltages at the nodes 9 and 10 is always kept at a fixed DC voltage, Vbias, irrespective of the value of the gain control voltage, Vagc. In the positive region of Vagc in FIGS. 7A to 7D, the voltage potential of the node 9 is higher than that of the node 10, while in the negative region of Vagc, the voltage potential of the node 10 is higher than that of the node 9. Note that an input signal source impedance 15 shown in FIG. 6 is 50Ω, and an output load impedance 16 of FIG. 6 is 5 kΩ.
How the gain changed when Vagc changed is represented by S21 of FIG. 7A. IIP3 was measured by conducting the simulations by inputting, at −50 dBm, two tone signals having center frequencies which were apart from the nominal measurement frequency by ±10 kHz. Namely in case of IIP3 measurement simulation at 50 MHz for instance, two −50 dBm tones having frequencies at 49.990 MHz and 50.010 MHz were input to the circuit in FIG. 6. The transition frequency fT of the transistors used in the simulations was 8 GHz. As the operating currents in the simulations, the current of the amplifier itself (the sum of the emitter currents of the transistors 3a and 3b in FIG. 6) was 9.6 mA, and the current in the negative feedback path (the emitter current of a transistor 62a or 62b) was 600 μA. The ratio between the operating current in the negative feedback path and the operating current of the differential amplifier at either side was set to 1:8. In FIGS. 7A to 7D, the bold line plots the simulation results at 550 MHz, the mid-size line plots at 300 MHz, and the thin line plots at 50 MHz, respectively.
As known from the characteristics of FIGS. 7A to 7D, though the circuit of the conventional art 1 had a gain variable width of about 60 dB, S11 abruptly degenerated in the negative region of Vagc, where the gain, S21, was decreased by 6 dB or more from the maximum gain, and IIP3 also degenerated simultaneously. The degeneration is because the amount of negative feedback also attenuated when the gain levels lowered.
A variable gain differential amplifier shown in a simulation circuit diagram of FIG. 8 as conventional art 2 is based on a technique published in the year 2003 in U.S. Pat. No. 6,600,371 B2. The conventional art 2 aims for solving the problem observed in the conventional art 1, i.e., the degeneration of the S11 and IIP3 characteristics when the gain lowers. Regardless of the current division ratio between two transistors 4a and 5a, and also equally between two transistors 4b and 5b in FIG. 8, the currents flowing across the resistors BM and BP have a constant value, allowing negative feedback of a constant amount to be always applied irrespective of the gain.
The results of operation simulations on the variable gain differential amplifier of FIG. 8 conducted by changing a gain control voltage will now be explained. FIGS. 9A to 9D are graphs of S21 (dB), NF (dB), S11 (dB), and IIP3 (dBm) observed at 50 MHz, 300 MHz, and 550 MHz. FIGS. 9A to 9D show the results of simulations on the circuit of FIG. 8, conducted with the same transistors, at the same operating currents, and under the same environmental conditions as used in the simulations on the circuit of FIG. 6, that are shown in FIGS. 7A to 7D. In the simulation of the circuit of FIG. 8, a DC voltage Vbias+Vagc was applied at the node 9, while a DC voltage Vbias−Vagc was applied at the node 10, giving a DC voltage difference across the nodes 9 and 10 by 2Vagc. Here, Vbias is a fixed DC voltage. Simulation results in FIGS. 9A to 9D were plotted against Vagc.
How the gain changed when Vagc changed is represented by S21 of FIG. 9A. IIP3 was measured by conducting the simulations by inputting, at −50 dBm, two tone signals having center frequencies which were apart from the nominal measurement frequency by ±10 kHz. In FIGS. 9A to 9D, the bold line plots the simulation results at 550 MHz, the mid-size line plots at 300 MHz, and the thin line plots at 50 MHz, respectively.
As known from the characteristics of FIGS. 9A to 9D, the use of the circuit of FIG. 8 makes it possible for negative feedback of a constant amount to be applied even when the gain changes, which means that the deficiency in the conventional art 1 is cured. However, the circuit of FIG. 8 has the following problems.
(1) The ratio of the maximum gain to the minimum gain is determined by the ratio of the resistance between a resistor AP (AM) and a resistor BP (BM) of FIG. 8. Therefore, even in order to achieve a maximum/minimum gain ratio of mere 40 dB, a ratio of resistance of 100:1 is required. Accordingly, if these resistors are made of the same-type resistors as each other, these resistors tend to occupy large areas on the die.
(2) In order that a gain variable amount of 40 dB may be secured, the resistance of the resistor BP (BM) takes a small value particularly in a high-frequency amplifier, from the reason described above. This makes it difficult to simultaneously achieve a sufficient input reflection characteristic, a sufficient noise figure characteristic, and a sufficient intermodulation distortion characteristic, with respect to a standard input signal source of 50Ω. Accordingly, this method can hardly realize a wide band variable gain amplifier, which has a gain variable width of 40 dB or wider.
For these reasons, a gain variable width that can be realized by the conventional art 2 over a wide frequency range is at most 20 dB. Even in that case, the best values of the noise figure, the distortion, and the input reflection characteristics tend to get worse than those of the conventional art 1. In the example the circuit of FIG. 8, the gain variable width was set to 20 dB, the load resistance (resistor AM+resistor BM) was set to 135Ω, which was equal to the resistance of the resistors 6a and 6b of FIG. 6. Under these conditions, the resistor BM had a resistance of 13.5Ω. In the circuit of FIG. 8, the resistance of the resistors BM and BP are one tenth of that of the resistors 6a and 6b of FIG. 6, meaning that the voltage amplitude of an inverting amplified signal at the input of negative feedback paths, that is, at the bases of transistors 62a and 62b in FIG. 8, is also degraded to one tenth of that given by the circuit of FIG. 6, when the gain of each amplifier is set to its maximum. Therefore, unless negative feedback resistors 12a and 12b have a lower resistance than that of those in the circuit of FIG. 6, it is impossible to achieve IIP3 and S11 characteristics similar to those of the circuit of FIG. 6 and to achieve negative feedback of a sufficient amount. However, the resistance of the resistors 12a and 12b cannot be reduced without a negative effect of the NF becoming larger. In the example of the circuit of FIG. 8, the negative feedback resistance was adjusted such that the NF at the maximum gain was equal to or smaller than about 4 dB. However, as apparent from the comparison between FIGS. 9A and 9D and FIGS. 7A and 7D, the maximum S21 of the circuit of FIG. 8 was larger by about 1 to 2 dB than that of the circuit of FIG. 6, and the IIP3 of the circuit of FIG. 8 at the maximum gain was lower by about 2 to 3 dBm than that of the circuit of FIG. 6.
The technique described in the following document can be raised as another method for improving the characteristics of a variable gain amplifying circuit. Unexamined Japanese Patent Application KOKAI Publication No. 2002-252532 discloses a variable gain amplifier, in which a plurality of variable gain amplifying circuits for attenuating the gain in response to an increase in the control voltage input from the outside are connected in parallel. In this variable gain amplifier, variable gain amplifying circuits that have lower emitter resistance than other amplifying circuits are earlier than other amplifying circuits in their gains being attenuated when the control voltage for the variable gain amplifying circuits increases. Because of this structure, the noise figure characteristic and the intermodulation distortion characteristic can be satisfied at the same time, says the Publication.
Unexamined Japanese Patent Application KOKAI Publication No. 2001-7667 describes a method for reducing high-frequency noise, by connecting a load resistor between a collector of a transistor at the non-output side and a power source and by connecting a capacitor between that collector and the ground.
FIG. 10 shows an example of a circuit of a balanced variable gain amplifier with a negative feedback effect, which aims for solving the problems of the conventional arts. This is an example of a circuit which is intended for solving problems such as the degeneration of the S11 and the IIP3 when the gain lowers, observed in the conventional art 1, the narrow gain variable width and the difficulty in securing a negative feedback amount without degenerating the NF at maximum gain, observed in the conventional art 2, etc. This circuit, which is provided with two negative feedback paths in the left-hand side and also in the right-hand side respectively, with the use of emitter followers (transistors 62a, 62b, 63a, and 63b) that are connected to transistors 4a, 4b, 5a, and 5b of FIG. 10, enables negative feedback of a constant amount to be always applied regardless of the gain levels.
FIGS. 11A to 11D show characteristics of the circuit of FIG. 10 observed at 50 MHz, 300 MHz, and 550 MHz, in a case where the voltages (2Vagc) across the bases of the transistors 4a and 5a and the bases of the transistors 4b and 5b were changed. FIGS. 11A to 11D show the results of simulations on the circuit of FIG. 10, conducted with the same transistors, at the same operating currents, and under the same environmental conditions as used in the simulations on the circuit of FIG. 6, that are shown in FIGS. 7A to 7D. In FIGS. 11A to 11D, the bold line plots the simulation results at 550 MHz, the mid-size line plots at 300 MHz, and the thin line plots at 50 MHz, respectively.
As known from the characteristics of FIGS. 11A to 11D, the input reflection characteristic and the distortion characteristic of the circuit of FIG. 10 were kept almost constant regardless of the changes of the gain, and improved as compared with the conventional art 1. Further, the circuit of FIG. 10 secured gain variable widths of 55 dB or wider, and had the S11 and the IIP3 kept almost constant regardless of the gain levels with almost no degeneration in the NF at the maximum gain, showing improvement compared with the conventional art 2. However, since the circuit of FIG. 10 is provided with two additional negative feedback paths with the use of the transistors 63a and 63b as emitter followers, it has a drawback that it consumes more current than the circuits of the conventional art 1 (FIG. 6) and the conventional art 2 (FIG. 8). The circuit of FIG. 10 includes one more negative feedback path (two more paths in the case of a balanced type), compared with the conventional arts 1 and 2. Therefore, the variable gain amplifier of FIG. 10 consumes current more than the variable gain amplifiers based on the conventional arts 1 and 2 that have similar performances, by about 1/10 to ¼ of the current of the variable gain amplifier itself.